1. Field of the Invention
The present invention relates generally to semiconductor technology and, more particularly, to self-aligned contact hole patterning and a hard mask spacer structure used during the self-aligned contact hole patterning.
2. Description of the Prior Art
As the pattern density increases and the feature size during printing of DRAM arrays becomes continuously smaller, the dimension of a contact hole or plug connecting component-to-component or layer-to-layer as well as the alignment margin for the device shrink.
In order to reduce the size of a contact hole formed through a photolithography process and to increase the alignment exactitude, a self-aligned contact is used. The self-aligned contact process may increase the alignment margin and reduce the contact resistance.
However, the prior art self-aligned method for patterning densely packed contact holes has shortcomings. For example, different contact hole profiles may occur, which may result in critical dimension (CD) control issue.